A demultiplexer routes one data input to one of several outputs, selected by control bits. A 1-to-4 demultiplexer has data input D, select inputs S1 and S0, and outputs Y0 through Y3. When D=1, exactly the selected output is 1; when D=0, all outputs are 0. K-maps derive the Boolean equation for each output and clarify how the select-bit polarity maps to the output index.
This guide builds the complete truth table, minimizes each output separately, checks the one-hot routing property, and compares a demultiplexer with a decoder. It also covers enable inputs and active-low outputs, where common notation mistakes can invert the intended behavior.
Define the routing behavior
There are four output destinations, so two select bits are enough. Use the convention S1S0=00 selects Y0, 01 selects Y1, 10 selects Y2, and 11 selects Y3. The data input D determines whether the selected line carries a 1 or whether all outputs remain 0. This definition should be written down before creating maps, because some diagrams reverse the select-bit order or number outputs differently.
The demultiplexer has three Boolean inputs and four outputs. Build one truth table with columns D,S1,S0,Y0,Y1,Y2,Y3. When D=0, the output vector is 0000 for all four select patterns. When D=1, the output vector is 0001,0010,0100, or 1000 depending on the selected line, if the outputs are written in Y3Y2Y1Y0 order. A table avoids ambiguity about how the vector is printed.
Write the truth table
| D | S1S0 | Y0 | Y1 | Y2 | Y3 | Selected path |
|---|---|---|---|---|---|---|
| 0 | 00 | 0 | 0 | 0 | 0 | Disabled by data |
| 0 | 01 | 0 | 0 | 0 | 0 | Disabled by data |
| 0 | 10 | 0 | 0 | 0 | 0 | Disabled by data |
| 0 | 11 | 0 | 0 | 0 | 0 | Disabled by data |
| 1 | 00 | 1 | 0 | 0 | 0 | D to Y0 |
| 1 | 01 | 0 | 1 | 0 | 0 | D to Y1 |
| 1 | 10 | 0 | 0 | 1 | 0 | D to Y2 |
| 1 | 11 | 0 | 0 | 0 | 1 | D to Y3 |
The output equations follow directly from the rows. Y0 is high only for D=1,S1=0,S0=0. Y1 is high only for D=1,S1=0,S0=1. Y2 requires D=1,S1=1,S0=0. Y3 requires D=1,S1=1,S0=1. In canonical SOP form, these are minterms of the three inputs, one minterm per output.
Minimize each output
For variables D,S1,S0 in that order, each output map has a single 1-cell, so no larger grouping is possible without including a required zero. The equations are:
Y1 = D S1′ S0
Y2 = D S1 S0′
Y3 = D S1 S0
Every equation contains D, so a low data input forces all outputs low. Each select combination appears exactly once. The select terms are the minterms of a 2-to-4 decoder, and the data input gates each decoded line. This is the structural identity of a demultiplexer: a decoder followed by data qualification.
Do not simplify by dropping a select literal. For example, D S1′ would assert both Y0 and Y1 whenever D=1,S1=0, regardless of S0. That would route the data to two outputs at once. The output functions are distinct because the select pattern must be fully decoded.
Verify data routing
Check the one-hot output property when D=1. At S1S0=00, only Y0's product has all literals true. At 01, only Y1 is true. At 10, only Y2 is true. At 11, only Y3 is true. When D=0, every product term contains a false D literal, so the output vector is 0000 regardless of select.
An algebraic check uses the sum of outputs: Y0+Y1+Y2+Y3 = D(S1′S0′+S1′S0+S1S0′+S1S0)=D. The decoded select terms are mutually exclusive and collectively exhaustive, so exactly one output is high when D=1. Pairwise products such as Y0Y1 are always zero because their select literals conflict.
If the circuit is used to drive asynchronous control lines, consider propagation hazards while select bits change. A binary select transition such as 01→10 changes two bits; unequal delays may briefly select an unintended output or none. If outputs must be glitch-free, register the selection, use a one-hot control, or analyze timing. The K-map equations describe stable input behavior.
Demultiplexer versus decoder
A 2-to-4 decoder has the same four select minterms but no separate data input. Its outputs are S1′S0′, S1′S0, S1S0′, and S1S0. A demultiplexer gates each decoder output with D. If D is tied high, a 1-to-4 demultiplexer behaves like a 2-to-4 decoder. If an enable E is included, the effective data term may be DE, so each output is qualified by both.
The difference matters in interfaces. A decoder converts a binary code into a one-hot line; a demultiplexer directs a signal value to the selected branch. In many logic diagrams the same gate structure performs both roles, but the semantics of the data and enable inputs should remain clear. A decoder's output is a selection indication; a demultiplexer's output carries the data value.
Add an enable input
Suppose the circuit has an enable E that must be high before any route is active. Then each function becomes E times its original output: Y0=ED S1′S0′, Y1=ED S1′S0, Y2=ED S1S0′, Y3=ED S1S0. If E=0, all outputs are 0. If E=1, behavior matches the original demultiplexer.
If the external enable is active-low, name it E′ or state “E_N is low to enable.” The equations then include E_N′. An ambiguous overbar can easily invert behavior in a schematic or HDL. Write a short truth table for enable asserted and deasserted, then test each selection case.
Some components provide an enable pin that affects outputs with a specified active polarity, while others provide complementary outputs. Do not assume the pin behavior from a generic logic equation; consult the device datasheet when implementing a specific chip. The abstract Boolean design and the package pin conventions are separate layers.
Handle active-low outputs
If outputs are active-low, the selected line is 0 and the unselected lines are 1. Let Y0_N through Y3_N denote active-low outputs. Then Y0_N=(D S1′S0′)′, with analogous expressions for the other lines. By De Morgan's law, Y0_N=D′+S1+S0. That form may map naturally to a NAND or NOR structure depending on available polarities.
Check the idle behavior explicitly. In the active-high design, D=0 forces all outputs to 0. In an active-low implementation, D=0 may force all outputs to 1, meaning none are asserted. The signal names should communicate whether assertion is high or low. A bar on the output label is not a cosmetic detail; it changes which voltage level denotes selection.
Build the one-hot selection terms
A gate-level implementation can share the inverted select signals S1′ and S0′. Generate those complements once, then use four three-input AND gates for the output products. If the device has only two-input gates, each product needs a small AND tree. A NAND implementation can form complemented products and use a final inversion or NAND stage, often taking advantage of De Morgan’s law. The best choice depends on available gate polarities and fan-in.
Sharing the select inversions saves gates, but it increases fanout: each select complement drives two output terms. For a small logic block this is usually insignificant; in a larger design, fanout and routing delay can matter. A synthesis tool may duplicate an inverter to improve timing, so a schematic with one shared inverter is not always the final mapped topology. Check the timing path from each select input to the output it controls.
Useful test cases
A short verification set should include D=0 with every select value, D=1 with each of the four select values, and at least one transition where D changes while the select is fixed. Also change both select bits, such as 01 to 10, and inspect whether an unintended output pulse is possible in the physical implementation. The stable truth table says only Y1 or Y2 should be high at the endpoints; unequal select delays can briefly produce another decode.
For a behavioral testbench, assert that the output vector is either 0000 when D=0 or one-hot when D=1. Then assert that the high bit index equals the select value. These properties are easier to maintain than eight unrelated expected vectors and will catch an accidental select-order swap. If the outputs are active-low, invert the assertions so “selected” means low and “unselected” means high.
Implementation checklist
- Specify select ordering. State which S1S0 pattern maps to each output number.
- Define data and enable behavior. Include disabled rows in the truth table.
- Derive one function per output. Use a consistent variable order.
- Check mutual exclusivity and coverage. At most one selected output should be active.
- Verify polarity. Distinguish active-high and active-low signals.
- Consider transitions. Multi-bit select changes can create short pulses in physical logic.
- Map to the target device. Check fan-in, timing, and pin conventions.
The four equations are simple minterms, but the design exercise teaches a broader method: translate a routing specification into a full truth table before simplifying. The K-map confirms that each selected output needs the data bit and the exact select pattern. Once enable and polarity are added, repeat the same process rather than relying on an assumed symbol convention.
Data routing versus one-hot control
When D is a data signal that changes over time, each selected output follows D while unselected outputs remain low. The outputs are not merely four static select indicators. That distinction matters if D is a clock, a pulse, or an asynchronous signal: routing it through combinational decode logic can create shortened or extra pulses when select changes. A demultiplexer is usually safest for ordinary data when selection is stable around the transfer interval.
If the goal is to create a one-hot control vector independent of data, use a decoder equation or set D permanently high. If the goal is to route a valid pulse, include an explicit enable or register the outputs according to the timing contract. Naming the source and destination signals in the specification helps prevent a decoder from being used where a data-path mux or registered crossbar is required.